发明名称 |
Format conversion circuit |
摘要 |
A format conversion circuit 100 includes a FIFO memory 101 for writing and reading video data VD in synchronization with a sampling clock CK, a header generation circuit 102 for generating an MPEG2-TS packet header, and a synchronous timing detection circuit 103 for detecting a horizontal synchronizing signal for the video data VD. The format conversion circuit 100 also includes a counter 104 which counts the number of bytes of packet header and the number of bytes of video data VD, and a switch 105 which selects the packet header until the counted number of bytes reaches four bytes, and then selects the video data read out of the FIFO memory 101.
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申请公布号 |
US2004165666(A1) |
申请公布日期 |
2004.08.26 |
申请号 |
US20030716791 |
申请日期 |
2003.11.19 |
申请人 |
KUBO HIROAKI;MURAKAMI MASAHIRO |
发明人 |
KUBO HIROAKI;MURAKAMI MASAHIRO |
分类号 |
H04N5/92;H04N5/00;H04N5/44;H04N5/46;H04N7/62;(IPC1-7):H04N7/12 |
主分类号 |
H04N5/92 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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