| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To control an information processing speed and power consumption by optimizing the number of execution cycles of a pipeline arithmetic operation according to a processing instruction and an internal condition, thereby by controlling the power voltage of a CPU. <P>SOLUTION: This information processor is provided with: a CPU 101 for processing an instruction by a pipeline arithmetic operation; and an internal condition measuring part 103 for measuring the internal condition of the device and generating an internal status signal S2. The CPU is provided with: an instruction decoding part 104 for decoding a read instruction, and for generating an instruction decoding information signal S1; an arithmetic control part 105 for generating an arithmetic control signal S3 based on the instruction decoding information signal from the instruction decoding part and generating a pipeline control signal S4 including the information of the number of execution cycles of the pipeline arithmetic operation based on the instruction decoding information signal and the internal status signal; and an arithmetic part 106 for executing a pipeline arithmetic operation of a kind corresponding to the arithmetic control signal in the number of execution cycles shown by the pipeline control signal from the arithmetic control part. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p> |
