发明名称 Flash array implementation with local and global bit lines
摘要 A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.
申请公布号 US2004165409(A1) 申请公布日期 2004.08.26
申请号 US20040784458 申请日期 2004.02.23
申请人 MICRON TECHNOLOGY, INC. 发明人 CHEVALLIER CHRISTOPHE
分类号 G11C7/18;G11C29/02;H01L27/115;(IPC1-7):G11C5/06 主分类号 G11C7/18
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