Method and apparatus for adjusting the performance of a synchronous memory system

摘要

A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.