发明名称 MULTIPLEXER AND DEMULTIPLEXER
摘要 PROBLEM TO BE SOLVED: To provide a multiplexer capable of maintaining high-speed and waveform quality and reducing the power consumption. SOLUTION: Level shift circuits 57 to 60, output polarity switching circuits 61 to 64, and output stop circuits 67 to 70 used in common to input circuits are located at a pre-stage of 2:1 multiplexers 75, 76. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004241797(A) 申请公布日期 2004.08.26
申请号 JP20030025710 申请日期 2003.02.03
申请人 FUJITSU LTD 发明人 NAKAYA YASUHIRO
分类号 H03K17/00;H03M9/00;H04J3/04;(IPC1-7):H03M9/00 主分类号 H03K17/00
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