Charge pump level converter (CPLC) for dual voltage system in very low power application

摘要

Recent efforts are underway to develop LSI circuits that operate at power supply voltages of 1-V or lower. It is a desire that this low core voltage circuits interface to 3.3-V I/O supply. A charge pump level converter for dual power supply application is proposed using low power and high speed interface to higher I/O supply. This circuit does not consume DC power it is suitable for low power and high speed interface and can be implemented using complementary metal-oxide-semiconductor (CMOS) fabrication processes.