Contact structure

摘要

Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate (106 and 108) having active electronic components (106a, 106b, 106c, 106d) such as ASICs mounted to an interconnection substrate (108) or incorporated therein, metallic spring contact element (110) effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) (102a, 102b, 102c, 102d) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements (110) may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate (108) is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller (116) and promulgating these signals over the relatively many interconnections between the ASICs and the DUTS.