| 摘要 |
PURPOSE: An apparatus for recovering a clock and a timing of digital packet data is provided to perform the clock recovery and the timing recovery of the data by outputting the carry and borrow signals through counting the detected phase error signal, thereby reducing the error. CONSTITUTION: An apparatus for recovering a clock and a timing of digital packet data includes a phase shifting unit(63), a phase lock loop, a counter(67) and a timing recovery unit. The phase shifting unit shifts the phase of the input data in response to the shift control signal to output the shifted input data. The phase lock loop generates the clock in response to the data outputted from the phase shifting unit and the phase error signal of the divided reference clock. The counter outputs the shift control signal to the phase shifting unit by dividing the carry and borrow signal level into various levels if the counted phase error signal becomes a predetermined level. And, the timing recovery unit recovers the timing of the data outputted from the phase shifting unit by using the reference clock.
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