| 摘要 |
A memory controller for a high-performance memory system has a pipeline architecture for generating control commands which satisfy logical, timing, and physical constraints imposed on control commands by the memory system. The pipelined memory controller includes a bank state cache lookup for determining a memory bank state for a target memory bank to which a control command is addressed, and a hazard detector for determining when a memory bank does not have a proper memory bank state for receiving and processing the control command. The hazard detector stalls the operation of the control command until the memory bank is in a proper state for receiving and processing the control command. The memory controller also has a command sequencer which sequences control commands to satisfy logical constraints imposed by the memory system, and a timing coordinator to time the communication of the sequenced control commands to satisfy timing requirements imposed by the memory.
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