发明名称 |
METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY |
摘要 |
A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
|
申请公布号 |
US6780708(B1) |
申请公布日期 |
2004.08.24 |
申请号 |
US20030382744 |
申请日期 |
2003.03.05 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
KINOSHITA HIROYUKI;SUN YU;BANERJEE BASAB;FOSTER CHRISTOPHER M.;BEHNKE JOHN R.;TABERY CYRUS |
分类号 |
H01L21/8242;H01L21/8246;H01L27/105;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8242 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|