发明名称 |
Two-transistor flash cell for large endurance application |
摘要 |
An nonvolatile memory device having improved endurance is comprised of an array of nonvolatile memory cells arranged in rows and columns. Each memory cell of each row is connected to a word line and a source select line, and each memory cell of each column connected to a first bit line and a second bit line. Each memory cell is composed of a first transistor and second transistor. The first and second transistors have control gate connected to the word line receive a word line voltage, a source connected the source select line to receive a source line voltage, and a floating gate onto which an electronic charge is placed representing a data bit stored within the nonvolatile memory device. The first transistor has a drain connected the first bit line to receive a first bit line voltage and the second transistor a drain connected to the second bit line to receive a second bit line voltage. Each memory cell has a floating gate connector joining the floating gate of the second transistor to the floating gate of the second transistor. The nonvolatile memory device has a voltage controller programs the each memory cell by programming the first transistor and reading the second transistor. Alternately the voltage controller employs a two step programming method by programming the first transistor for a short period of time and then programming the second transistor for second short period of time and then reading from the second transistor.
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申请公布号 |
US6781881(B2) |
申请公布日期 |
2004.08.24 |
申请号 |
US20020323982 |
申请日期 |
2002.12.19 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
CHIH YU-DER |
分类号 |
G11C11/22;G11C16/04;H01L21/28;H01L21/336;H01L21/8247;H01L27/115;H01L29/423;H01L29/792;(IPC1-7):G11C16/04 |
主分类号 |
G11C11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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