发明名称 |
Apparatus and method for processing data using a merging cache line fill to allow access to cache entries before a line fill is completed |
摘要 |
A data processing system includes a processor core, a cache memory and a cache controller which operate to allow data accesses to a cache line for which a pending cache linefill operation exists to be serviced for those data words within the cache line that are valid at a particular point in time. One or more status bits are provided in association with each cache line indicating whether a line fill is pending for that cache line. The old data may be manipulated up to the point where the first new data is returned. New data items may be read once they have been written into a victim cache line even though the cache linefill is not completed. Stores to the victim cache line may be made via a fill buffer even though the linefill is still pending. The cache memory may include a content addressable memory (CAM) and the cache memory and controller may support a hit under miss operation.
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申请公布号 |
US6782452(B2) |
申请公布日期 |
2004.08.24 |
申请号 |
US20010011310 |
申请日期 |
2001.12.11 |
申请人 |
ARM LIMITED |
发明人 |
WILLIAMS, III GERARD RICHARD |
分类号 |
G06F12/08;(IPC1-7):G06F13/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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