| 摘要 |
An apparatus comprising a control circuit and a generation circuit. The control circuit may be configured to generate a mask signal, a unique counter control signal, and an incremented state signal in response to an address signal and a counter control signal. The generation circuit may (i) comprise an internal counter register and (ii) be configured to generate an output address in response to the mask signal, the unique counter control signal, and the incremented state signal. The mask signal may be configured to selectively mask the internal counter register.
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