TIMER CIRCUIT, SPECIALLY ENABLING A STABLE OPERATION BY GENERATING A COUNTER ENABLE SIGNAL, AND EFFECTIVELY CONDUCTING A TEST FUNCTION BY PREDICTING A COUNTING VALUE OF A TIMER

摘要

PURPOSE: A timer circuit is provided to generate a counter enable signal based on an input control clock signal while pre-scaling a timer, thereby reducing a wrong operation without an invasion upon a clock network and guaranteeing a stable timer function. CONSTITUTION: A test controller(4) outputs a test mode signal(TM) to set a test mode in a timer. A pre-scaler(5) generates a demultiply signal corresponding to a pre-scale selection signal(P-SEL), outputs an enable signal(EN) for one cycle of an input clock signal(CLK) in a rising edge part of the demultiply signal, and operates in the test mode or a normal mode, depending on whether the test mode signal(TM) is inputted. A counter(6) counts values destined in a falling edge of the input clock signal(CLK) whenever being enabled by the enable signal(EN), and operates as a nibble counter whenever a counter control signal(CS) is supplied.