| 摘要 |
PROBLEM TO BE SOLVED: To provide a technique for dimensionally reducing a semiconductor device with punch-throughs prevented in spite of an intra-well gap reduced to the submicron scale. SOLUTION: On a p-type semiconductor substrate 1, a p-well 4 is sandwiched in between two n-wells 2 and 3, and a p-well 5 or a p-type epitaxial layer is provided beneath the two n-wells 2 and 3 and the p-well 4. By using this design, punch-throughs are prevented from occurring in between the two n-wells 2 and 3 and the gap between the two n-wells 2 and 3 is narrowed down. COPYRIGHT: (C)2004,JPO&NCIPI
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