发明名称 METHOD FOR CREATING SYSTEM DIAGRAM OF LOGIC CIRCUIT, AND DEVICE FOR CREATING SYSTEM DIAGRAM OF LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method for creating a system diagram of a logic circuit that shortens the time to correct the arrangement and connection of logic blocks and enables even a third person to quickly understand the operation of a logic circuit. SOLUTION: A logic circuit with a plurality of interconnected logic blocks includes an input signal 1A showing a signal input into the logic circuit, an output signal 1B showing a signal output from the logic circuit, logic blocks 2A to 2D that are functional small-scale circuit divisions of the logic circuit arranged according to given block arrangement rules, arrow signals 3A to 3E showing by arrows the directions of signals connected to the logic blocks 2A to 2D, and node indications showing branches and junctions of the arrow signals 3A to 3D. The logic blocks 2A to 2D are arranged under the shortest length of the arrow signals 3A to 3E. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004234295(A) 申请公布日期 2004.08.19
申请号 JP20030021560 申请日期 2003.01.30
申请人 MITSUBISHI ELECTRIC CORP 发明人 KIMIJIMA TATSUYA;MASUHAMA KAZUO
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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