发明名称 TIMING ANALYSIS METHOD AND TIMING ANALYSIS PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a timing analysis method and a timing analysis program, capable of executing timing analysis in a short time while maintaining the estimation accuracy high for the delay information about actual wiring. SOLUTION: RC information about each hierarchical block is extracted (step S11), top-level RC information with only a portion wherein all the hierarchical blocks are excepted from the whole chip as a target is extracted (step S12), delay calculation of the whole chip is executed (step S13), a boundary model of each the hierarchical block is produced (step S14), hollowing of the delay information (step S15) and hollowing of timing restriction (step S16) are executed, production of a net list of an analysis target (step S17) is executed, the timing analysis is executed (step S18), and all the hierarchical blocks are totally flat-developed without exception and is executed with the timing analysis (step S19). COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004234193(A) 申请公布日期 2004.08.19
申请号 JP20030020383 申请日期 2003.01.29
申请人 KAWASAKI MICROELECTRONICS KK 发明人 KOBAYASHI TAKESHI
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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