| 摘要 |
PROBLEM TO BE SOLVED: To reduce the capacity of a character conversion table (S-box) while maintaining the performance of an AES encryption processing circuit. SOLUTION: In an AES encryption processing device, one element of eight bits on an input state 101 is selected by a column multiplexer 102 and a row multiplexer 104. The selected element is character converted by an S-box table 105 and inputted to a Galois field multiplier 107. 4 parallel multiplication of the output of the S-box table 105 and the output of a coefficient table 106 is carried out by the Galois field multiplier 107, and 32-bit output is stored in an arithmetic result register 108. The output of the arithmetic result register 108 is added to a cumulative register 110 by the Galois field adder 109 and stored in the cumulative register 110. COPYRIGHT: (C)2004,JPO&NCIPI
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