发明名称 A METHOD FOR MAKING NANOSCALE WIRES AND GAPS FOR SWITCHES AND TRANSISTORS
摘要 A method for forming first and second linear structure of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has as asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.
申请公布号 WO03083928(A3) 申请公布日期 2004.08.19
申请号 WO2003US07572 申请日期 2003.03.13
申请人 HEWLETT-PACKARD COMPANY 发明人 CHEN, YONG;WILLIMAS, R STANLEY,
分类号 B82B3/00;G11C13/00;H01L21/00;H01L21/20;H01L21/28;H01L21/3065;H01L21/308;H01L21/3213;H01L21/335;H01L21/336;H01L21/44;H01L21/82;H01L27/10;H01L29/06;H01L29/423;H01L29/76;H01L29/775;H01L29/786;H01L29/94;H01L31/0328;H01L31/113 主分类号 B82B3/00
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