RECEIVING CIRCUIT AND TRANSMITTING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a transmitting/ receiving circuit for communication in which the operating speed of a clock synchronization digital circuit is enhanced to the maximum speed of flip-flop and the occurrence of a jitter is suppressed.

SOLUTION: A clock signal synchronized with data with f1/n[Hz] of frequency is made into n-fold clock frequency by a multiplier 3 and used as a trigger of the flip-flop with f1[b/s] of the operating speed in the clock synchronization digital circuit 4. The multiplier avoids an effect of lowering of the operating speed due to wiring capacity by arranging the clock signal with f1[hz] in the vicinity of the flip-flop using the clock signal as the trigger. Thus, the maximum operating speed of the transmitting/receiving circuit determined by an operating frequency of the clock synchronization digital circuit is enhanced to the maximum operating speed of the flip-flop. Since a margin is made in frequency band design of a clock signal processing circuit, power consumption and phase noise are reduced and a control frequency range is expanded.

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