NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

摘要

PROBLEM TO BE SOLVED: To provide EEPROM device where a high voltage is applied to a chip when a memory cell is operated. SOLUTION: A first N well 11 is formed on the surface area of a cell array area substrate and a second N well 12 is formed on the third surface area of a peripheral circuit area substrate on a P type semiconductor substrate 10. An EEPROM memory cell is formed on a first P well 13, and a first NMOS transistor is formed on a second P well 14. In addition, a second NMOS transistor is formed on the second surface area of the P type semiconductor substrate in the peripheral circuit area, and a PMOS transistor is formed on the second N well 12. The concentrations of the impurities of the first P well 13 and the second P well 14 are controlled by the characteristics of the formed MOS transistor. Further, the second NMOS transistor having a resistance against the high voltage is directly formed on the P type substrate. COPYRIGHT: (C)2004,JPO&NCIPI