发明名称 |
Circuitry to reduce PLL lock acquisition time |
摘要 |
A phase locked loop, PLL, is described with multiple parallel chnrge pumps that are selectively disabled as phase lock is approached. A lock detection circuit is described that enabled reference currents to be fed to the parallel charge pumps. The error signal from a phase detector is arranged as UP and a DOWN signals that are averaged in the lock detector. When the average error is large, all the reference currents feed the charge pumps that provide a high loop gain to reduce the lock time. As the lock becomes closer selective reference currents are disabled to reduce loop gain so that a smooth transition to lock is made. Selectively switching currents into a low pass filter that usually follows a charge pump in a PLL circuit automatically reduces switching noise by the operation of the low pass filter.
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申请公布号 |
US2004160281(A1) |
申请公布日期 |
2004.08.19 |
申请号 |
US20040780493 |
申请日期 |
2004.02.17 |
申请人 |
MCDONALD JAMES J.;HULFACHOR RONALD B. |
发明人 |
MCDONALD JAMES J.;HULFACHOR RONALD B. |
分类号 |
H03L7/089;H03L7/095;H03L7/107;H03L7/18;(IPC1-7):H03L7/00 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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