| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a data arithmetic unit capable of realizing an efficient arithmetic processing by solving waste in memory access time. <P>SOLUTION: This data arithmetic unit comprises a trigger latch 2; a timing generation part 3; an address generation part 4; a delay part 5; a data updating part 6 having a read latch 9, an arithmetic part 10 and a write latch 11; a data updating part 7 having a read latch 12, an arithmetic part 13 and a write latch 14; and a memory 8. The operations of the data updating parts 6 and 7 are simultaneously executed while keeping a phase difference corresponding to a determined clock number, whereby data operation can be performed while simultaneously driving the data updating parts 6 and 7 at clocks differed in phase, and an efficient arithmetic processing can be realized. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
