| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To divide an interface for managing interconnection between a PCI bus and peripheral devices into a plurality of blocks, and limit supply of operating clocks to unused blocks. <P>SOLUTION: OR circuits 16 each produce the logical sum of a STOP_CLK signal 15 and a clock from a clock oscillator to control a start/stop of clock transmission. Specifically, when the STOP_CLK signal 15 is High, the logical sum output is High to stop the clock. An initiator control part itself can determine whether or not to start its own access, and thus determines the timing to set the STOP_CLK signal 15 to Low. After a completion signal of data transfer on the PCI bus is detected, the STOP_CLK signal 15 is set to High again to stop the clock. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p> |
