发明名称 |
Clock recovery circuit |
摘要 |
A clock recovery circuit for establishing bit synchronization with a received signal. The clock recovery circuit comprises a conventional early-late gate circuit and a loop filter. The loop filter receives an output signal of an early sample circuit included in the early-late gate circuit and an output signal of a late sample circuit included in the early-late gate circuit to generate a control signal output. The control signal is input to a clock-produced device included in the early-late gate circuit. The clock-produced device generates a clock at an ideal impulse-produced time controlled by the control signal. The ideal impulse-produced time is a middle point of the n-th symbol of the received signal.
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申请公布号 |
US2004161071(A1) |
申请公布日期 |
2004.08.19 |
申请号 |
US20030366367 |
申请日期 |
2003.02.14 |
申请人 |
CHEN JIU-CHENG;YU CHAO-CHIEH |
发明人 |
CHEN JIU-CHENG;YU CHAO-CHIEH |
分类号 |
H04L7/033;(IPC1-7):H03D3/24 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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