| 摘要 |
Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.
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