发明名称 |
Semiconductor device |
摘要 |
A logic circuit block and a memory circuit block are provided on a semiconductor chip. A timing adjustment circuit block for adjusting the propagation timing of signals is provided on a line between the circuit blocks. A timing adjustment circuit unit includes: a delay element block including a plurality of delay elements for adding different delay amounts to the inter-block signals; a counter circuit block for receiving a timing adjustment control signal from the timing adjustment circuit block; and a fuse circuit block in which a fuse is melted down based on a fuse information signal held by the counter circuit block after a timing verification and which replaces the function of the counter circuit block.
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申请公布号 |
US2004160256(A1) |
申请公布日期 |
2004.08.19 |
申请号 |
US20040773315 |
申请日期 |
2004.02.09 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KURODA NAOKI;SHIRAHAMA MASANORI |
分类号 |
H01L21/822;H01L21/00;H01L21/82;H01L27/00;H01L27/04;H03H11/26;(IPC1-7):H03H11/26 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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