发明名称 |
Clock control in sequential circuit for low-power operation and circuit conversion to low-power seqential circuit |
摘要 |
Clock control of a sequential circuit is realized with the assumptions that stop of a clock is impossible due to the specifications, and feedback of the output of a memory element does not exist. To this end, the sequential circuit includes a variation detector for detecting a variation occurred in the content of any of master cells which are memory elements included in a master cell group to output a clock control signal, and a clock pulse generator for receiving the clock control signal to generate a clock pulse and supplying the clock pulse to a slave cell which is a memory element included in a clock domain and whose input is varied when the content of any of the master cells which are memory elements included in the master cell group is varied.
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申请公布号 |
US2004160852(A1) |
申请公布日期 |
2004.08.19 |
申请号 |
US20040776287 |
申请日期 |
2004.02.12 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
SASAGAWA YUKIHIRO |
分类号 |
G06F17/50;G06F1/10;G11C7/22;(IPC1-7):G11C8/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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