| 发明名称 |
SEMICONDUCTOR DEVICE AND ARRANGEMENT METHOD OF DUMMY PATTERN THEREOF |
| 摘要 |
PROBLEM TO BE SOLVED: To provide a dummy pattern for chemical mechanical polishing (CMP) of a metal where high uniformity is provided in a chip and high chipping resistance is provided for a scribe line. SOLUTION: The square dummy patterns disposed in a knight jump manner automatically generable at high uniformity in a chip, and the rectangular dummy patterns in lattice arrangement which have high chipping resistance is formed in a scribe line area. In the case with multilayer wiring, dummy patterns on the scribe lines in different wiring layers are connected together with a via. COPYRIGHT: (C)2004,JPO&NCIPI |
| 申请公布号 |
JP2004235357(A) |
申请公布日期 |
2004.08.19 |
| 申请号 |
JP20030021084 |
申请日期 |
2003.01.29 |
| 申请人 |
NEC ELECTRONICS CORP |
发明人 |
MATSUMOTO AKIRA;FUKASE TADASHI;IGUCHI MANABU |
| 分类号 |
H01L23/52;H01L21/301;H01L21/3205;H01L21/321;H01L21/44;H01L21/70;H01L21/768;H01L21/78;H01L21/82;H01L21/822;H01L23/48;H01L23/544;H01L23/58;H01L27/04;(IPC1-7):H01L21/320 |
主分类号 |
H01L23/52 |
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