| 摘要 |
In each processor of a plurality of processors provided in one chip, an instruction to be executed by an instruction code inputted thereto is to be determined uniquely, based on input history of the instruction codes, from the plural instructions assigned to the instruction codes by an decoder circuit. Accordingly, every instruction can be expressed by a short instruction code length, with one instruction code corresponding to the plural instructions, as well as different kinds of instructions can be executed, based on the input history of the instruction codes, by the same instruction code.
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