LAYOUT OF INTEGRATED STRUCTURE FOR INSTRUCTION EXECUTION UNIT

摘要

PROBLEM TO BE SOLVED: To perform layout of a semiconductor with each part integrated on a semiconductor chip to save the chip area. SOLUTION: This unit comprises a data subsidiarity checker 108 for receiving a group of command address signals and transmitting subsidiarity information through a subsidiarity output line; a tag assignment logic 122 for receiving the subsidiarity information through the subsidiarity output line and transmitting tag information through a tag output line; and a register file port mutliplexer 124 for receiving the tag information through the tag output line and further transferring the tag information to the register file address port of a register file. The tag output line is directly guided to the register file port multiplexer in a substantially linear route, and arranged in a central channel, and at least part of the tag assignment logic is disposed on the opposed side of the central channel. COPYRIGHT: (C)2004,JPO&NCIPI