发明名称 High speed multiple port data bus interface architecture
摘要 A bus controller card capable of communicating high speed data between at least one host computer and at least one peripheral comprises a first bus segment connected between a first host connector, a first expander, a first card controller, a second expander, and a second host connector. A second bus segment extends from the first expander to a first backplane connector. A third bus segment extends from the second expander to a second backplane connector. At least one monitor bus segment is provided on the backplane to directly connect the first card controller to a second card controller on another bus controller card in the system. Each bus controller card is capable of determining whether cable connections to the bus interface card are properly mated; whether to enable an expander on the bus controller card; whether the bus controller card has primary or secondary status; and generating a signal to reset other components, including the other bus controller card, when one or more prespecified events are detected.
申请公布号 US2004162927(A1) 申请公布日期 2004.08.19
申请号 US20030370358 申请日期 2003.02.18
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 BENSON ANTHONY JOSEPH;DEBLANC JAMES J.
分类号 G06F13/00;G06F13/38;(IPC1-7):G06F13/00 主分类号 G06F13/00
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