| 摘要 |
PURPOSE: A digital equalizer is provided to reduce an array area of a high-bit equalizer by using a half-size multiplier. CONSTITUTION: A digital equalizer includes a delay buffer, a first selector, a first storage unit, a second storage unit, an n/2 bit multiplier, an adder/subtracter, a sub-accumulator, and an accumulator. The delay buffer(101-104) is used for storing pulse code modulation data and equalized pulse code modulation data according to a buffer enable signal. The first selector is used for outputting selectively the pulse code modulation data or the output data of the delay buffer according to the first MUX selection signal. The first storage unit stores plural output data of different logic values corresponding to the output data of the first selector according to a register control signal. The second storage unit stores plural output data of different logic values corresponding to plural filter coefficients according to a register control signal. The n/2 bit multiplier(112) is used for multiplying the output data of the first selector by the output data of the second selector according to the second MUX selection signal. The adder/subtracter(115) is used for adding and subtracting the pulse code modulation data, the output data of the n/2 bit multiplier, the equalized pulse code modulation data, and the output data of the sub-accumulator. The sub-accumulator(117) is used for storing the output data of the adder/subtracter and outputting the arbitrary accumulated output data according to an accumulation control signal. The accumulator(116) is used for accumulating the output data of the adder/subtracter according to the accumulation control signal and outputting the equalized pulse code modulation data.
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