发明名称 |
Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop |
摘要 |
A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.
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申请公布号 |
US6777977(B1) |
申请公布日期 |
2004.08.17 |
申请号 |
US20020137729 |
申请日期 |
2002.05.01 |
申请人 |
ACTEL CORPORATION |
发明人 |
REYNOLDS ALAN B.;REYNOLDS ANDREW W.;HECHT VOLKER |
分类号 |
H03K19/177;(IPC1-7):G06F7/38 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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