发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD OF CONTROLLING STRESS IMPRESSION AMOUNT ONTO SEMICONDUCTOR CHIP
摘要 PROBLEM TO BE SOLVED: To freely control a stress impression amount and impression timing for each block. SOLUTION: Electric power source switches 201, 202, 203 are provided respectively in circuit blocks 101, 102, 103, the electric power source switches are respectively controlled individually during burn-in inspection to regulate electric power source supply times, i.e. stress amounts, to the respective blocks. The stress of required enough amount is impressed to the circuit block requiring the longest stress impression time, and an excess stress is prevented from being impressed to the other circuit blocks, by this manner. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004226220(A) 申请公布日期 2004.08.12
申请号 JP20030013991 申请日期 2003.01.22
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAWANO TAKESHI
分类号 G01R31/26;G01R31/30;H01L21/822;H01L27/04;(IPC1-7):G01R31/30 主分类号 G01R31/26
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