| 摘要 |
PROBLEM TO BE SOLVED: To provide a readout circuit that reduces weight of bus cycles at a processor side and accelerates readout speed of the processor to a random accessible flash memory in a semiconductor memory device equipped with the memory. SOLUTION: The readout circuit is provided with; an address decoder circuit, which inputs an address obtained by shifting an external address value to a low-order bit direction by one bit as the address signal of a first memory circuit, and which inputs an address obtained by shifting a value subtracting one from the external address value to the low-order bit direction by one bit as the address signal of a second memory circuit; and a control signal generation circuit, which activates an output validation signal sent out to one of the first and second memory circuits when the external address value is an even number, and which activates an output validation signal sent out to the other of the first and the other of the second memory circuit when the external address value is an odd number. COPYRIGHT: (C)2004,JPO&NCIPI
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