| 摘要 |
PURPOSE: A ferroelectric memory is provided to suppress the generation of read error of data by increasing read margin. CONSTITUTION: A memory cell array has a plurality of memory cells(1) arranged in a matrix and a read voltage application circuit(41) for applying a read voltage VR to the word lines WL0 to WL2 in data reading. One port of a ferroelectric capacitor(2) of each memory cell is connected to word lines(WL0-WL2), and another port of the ferroelectric capacitor is connected to bit lines(BL0-BL2). The ferroelectric capacitor includes a ferroelectric film having capacitances(Cf0,Cf1) in an initial state. Each word line is connected to a row decoder(31), and each bit line is connected to a column decoder(32). A row address and a column address are inputted to an address pin(33). The row address and the column address are transmitted to an address latch(34) from the address pin. Then, the row address is transmitted to the row decoder through an address buffer(35), and the column address is transmitted to the column decoder through the address buffer.
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