| 摘要 |
PROBLEM TO BE SOLVED: To provide a data transfer controller by which occurrence frequency of interruption to a central processing unit is reduced without restricting the storage capacity of a buffer memory housed in a peripheral module at a transfer destination. SOLUTION: The data transfer controller for controlling data transfer between a main memory having arbitrary storage capacity and first-in/first-out allowed to function as a buffer for data transfer housed in the peripheral module comprises: a transfer frequency register 303 setting a value being the value indicative of the transfer frequency of the data and complying with the storage capacity of the first-in/first-out and a transfer frequency register 304 setting a value complying with the amount of the data stored on the main memory, and controls the data transfer based on the value of the transfer frequency register 303 and outputs an interruption signal to the central processing unit based on the value of the transfer frequency register 304. COPYRIGHT: (C)2004,JPO&NCIPI
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