| 摘要 |
A field region forming a transistor is provided in a direction crossing a word line and a bit line. A bit line contact is provided corresponding to each bit line in a row direction. Storage node contacts are provided in alignment corresponding to respective columns in the row direction. The size of a basic cell region for forming a single memory cell can be set to 2.F.3.F. Here, F represents a minimum design size. Accordingly, memory cells in a twin cell mode DRAM storing one bit of data with two memory cells can be reduced in size.
|
