发明名称 |
Balanced sense amplifier control for open digit line architecture memory devices |
摘要 |
A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.
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申请公布号 |
US2004158690(A1) |
申请公布日期 |
2004.08.12 |
申请号 |
US20040775231 |
申请日期 |
2004.02.11 |
申请人 |
GRAHAM SCOT M.;DERNER SCOTT J.;PORTER STEPHEN R. |
发明人 |
GRAHAM SCOT M.;DERNER SCOTT J.;PORTER STEPHEN R. |
分类号 |
G11C7/06;G11C7/08;G11C11/4091;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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