Semiconductor device, particularly dynamic random access memory device, comprises semiconductor substrate, wirings, insulating spacers, self-aligned contact pads, interlayer dielectric layer, and selective epitaxial silicon layer

摘要

A semiconductor device comprises: semiconductor substrate (100); wirings formed on the substrate and separated from each other; insulating spacers formed on sidewalls of the wirings; self-aligned contact pads (116a, 116b) having portions of a second conductive layer; interlayer dielectric layer formed on the contact pads, wirings, and substrate; and selective epitaxial silicon layer (134) formed on contact pad exposed through the contact holes. A semiconductor device comprises: semiconductor substrate; wirings formed on the substrate and separated from each other; insulating spacers (128) formed on sidewalls of the wirings; self-aligned contact pads having portions of a second conductive layer; interlayer dielectric layer formed on the contact pads, wirings, and substrate; and selective epitaxial silicon layer formed on the contact pad exposed through the contact holes to cover the insulating mask layer pattern (126). The wirings include first conductive layer pattern and insulating mask layer pattern formed on the first conductive layer pattern. The self-aligned contact pads are in contact with surfaces of the insulating spacers to fill a gap between the wirings. The interlayer dielectric layer includes contact holes that expose the contact pads. An independent claim is included for a method of manufacturing a semiconductor device comprising forming wirings separated from each other on a semiconductor substrate, forming insulating spacers on sidewalls of the wirings, forming self-aligned contact pads including portions of a second conductive layer, forming an interlayer dielectric layer on the substrate where the contact pads are formed, partially etching the interlayer dielectric layer to form contact holes exposing the contact pads, and forming a selective epitaxial silicon layer on the contact pads exposed through the contact holes to cover the insulating mask layer pattern.