| 摘要 |
A shift register is provided, for example, for use in scan and data line drivers (2, 3) for an active matrix liquid crystal display. The shift register comprises X stages (31-35), where X is an integer greater than 3. A clock signal generator (51) supplies Y-phase clock signals (CK1-CK3), where Y is greater than 2. Each intermediate stage (32-34) receives a set enable signal from the immediately preceding stage output, is set by the start of a clock pulse in the presence of the enable signal, and is reset by the end of the clock pulse. In order to provide bi-directional operation, each intermediate stage (32-34) also receives set enable signals from the immediately succeeding stage output. The clock signal generator (51) supplies clock pulses in a first order for shift register operation in the forward direction and in the reverse order for shift register operation in the reverse direction. <IMAGE>
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