| 摘要 |
PURPOSE: The layout arrangement method of most effective semiconductor connection parallel MOS, transistor is provided to satisfy a model parameter for circuit simulation, enhance the performance, and reduce a risk by arranging individual transistors in parallel. CONSTITUTION: A common node of a source and a drain is divided into individual transistors. The transistors are arranged in parallel in a CMOS process. The transistors are arranged in parallel in a logic process. The transistors are arranged in parallel in a system LSI process. The transistors are arranged in parallel in a chemical compound semiconductor process. The transistors are arranged in parallel in a mixing fabrication process of the CMOS, the logic, the system LSI, and the chemical compound semiconductor processes.
|
