发明名称 |
Field-programmable gate array architecture |
摘要 |
A field-programmable gate array (FPGA) is disclosed. A two-by-two array of FPGA tiles is surrounded by a JTAG interface, a Configuration interface and a BIST interface. Each interface is located adjacent to an outer edge of the two-by-two array of FPGA tiles. A plurality of boundary scan register chains are located adjacent to an outer perimeter of the two-by-two array of FPGA tiles and the JTAG, Configuration and BIST interfaces. A plurality of RAM blocks are located adjacent to an outer perimeter of the plurality of boundary register scan chains. A plurality of input/output pad rings is located adjacent to an outer perimeter of the plurality of ram blocks.
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申请公布号 |
US6774672(B1) |
申请公布日期 |
2004.08.10 |
申请号 |
US20020334339 |
申请日期 |
2002.12.30 |
申请人 |
ACTEL CORPORATION |
发明人 |
LIEN JUNG-CHEUN;FENG SHENG;LIU TONG |
分类号 |
H03K19/177;(IPC1-7):H03K19/173 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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