发明名称 Video overlay processor with reduced memory and bus performance requirements
摘要 A method of video overlay processing and a system thereof. On-screen display (OSD) data for generating an image on a display device are downloaded to an OSD unit on an integrated circuit. The OSD data are downloaded in bursts separated by gaps. During the gaps, overlay data for generating an overlay on the image are downloaded to an overlay unit on the integrated circuit. The overlay data are divided into portions so that the overlay data can be downloaded in the time between bursts of OSD data. Generally, the amount of overlay data downloaded during a gap is sufficient for generating enough of the overlay until the next gap occurs and the next portion of overlay data is downloaded. Consequently, the size of the memory residing on the integrated circuit for storing overlay data can be reduced to the size needed to store only a portion of the overlay. Furthermore, the bus bandwidth for the OSD is more efficiently utilized.
申请公布号 US6774918(B1) 申请公布日期 2004.08.10
申请号 US20000605967 申请日期 2000.06.28
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V. 发明人 MUTH PETER VALENTINE
分类号 H04N5/445;(IPC1-7):G09G5/00 主分类号 H04N5/445
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