发明名称 Memory with shared bit lines
摘要 A memory block comprising a network of memory cell rows and columns, each memory cell being connected to a word line and at least one bit line, in which at least two word lines are associated with each row, and at least two adjacent columns share at least one same bit line, two memory cells of the two adjacent columns belonging to a same row being connected to different word lines.
申请公布号 US6775179(B2) 申请公布日期 2004.08.10
申请号 US20020232256 申请日期 2002.08.30
申请人 DOLPHIN INTEGRATION 发明人 COVAREL HERVE;GAUBERT SEBASTIEN
分类号 G11C11/41;G11C8/14;G11C11/418;G11C11/419;H01L21/8244;H01L27/11;(IPC1-7):G11C11/00 主分类号 G11C11/41
代理机构 代理人
主权项
地址