发明名称 Semiconductor design/fabrication system, semiconductor design/fabrication method and semiconductor design/fabrication program
摘要 A semiconductor design/fabrication system which combines a plurality of function blocks and arranges the combined function blocks on a chip, comprising: a function block selector which selects the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known; a chip information calculator which calculates a sum of the critical areas on each of the selected function blocks; an yield calculator which calculates an yield based on a calculation result of the chip information calculator and defect occurrence rate information of a chip fabrication line; a cost delivery time information calculator which calculates information relating to fabrication cost and delivery time of the chip based on a calculation result of the yield calculator and fabrication management information relating to cost and fabrication period of the chip fabrication line; and a combination selector which selects a combination of the function blocks constituting the chip based on the information relating to the fabrication cost and the delivery time of the chip calculated by the cost delivery time information calculator.
申请公布号 US6775816(B2) 申请公布日期 2004.08.10
申请号 US20020327114 申请日期 2002.12.24
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SATO YOSHIYUKI;SUGIMOTO SHIGEKI;AKIYAMA TATSUO
分类号 H01L21/66;(IPC1-7):G06F17/50 主分类号 H01L21/66
代理机构 代理人
主权项
地址