发明名称 Clock synchronization logic
摘要 A method and apparatus for synchronizing actions of two circuits or two parts of one circuit where each circuit utilizes a different clock signal. More than one clock signal are derived from a master clock signal and run at the same frequency but have an unknown or variable phase difference. The invention solves the problem of coupling two clocked circuits where synchronization is required to properly read or sample a signal from a data line connecting the two circuits. An error window is defined during which sampling is suppressed, for example to avoid sampling during data transitions. The method of apparatus involves time shifting a pseudo-signal to generate two time-shifted signals and then defining the error window as the time during which the two time-shifted signals differ from one another.
申请公布号 US6774823(B1) 申请公布日期 2004.08.10
申请号 US20030349204 申请日期 2003.01.22
申请人 ANALOG DEVICES, INC. 发明人 SCHAFFERER BERND
分类号 G06F1/12;H03L7/081;H03L7/087;H03L7/091;H04L7/00;(IPC1-7):H03M7/00 主分类号 G06F1/12
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