Dual threshold buffer with hysteresis

摘要

The present invention is directed to a buffer having dual thresholds. The buffer has an input terminal and an output terminal and comprises a current source, first through fourth transistors, a current mirror, and an output driver. The buffer uses an "analog" topology to achieve accurate buffering when the thresholds of applied signals are not centered about the mid-supply range. The buffer is useful (among other circuits) in analog and mixed circuit integrated circuits that have relatively high voltage supply levels and signals having logic thresholds that are not centered about the mid-supply level. The buffer uses feedback from the output to achieve hysteresis.