发明名称 Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor
摘要 A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by first and second dielectric layers. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first and second dielectric layer. The two layer structure is an equal potential structure and includes a conductive coupling between the two layers. In one embodiment, the back plate of the capacitor is formed from a metal layer. A third and fourth dielectric layers surround the first two-layer conductive structure. A second two-layer equal potential conductive structure surrounds the third and fourth dielectric layers. In one embodiment, the second two-layer equal potential conductive structure comprise an interconnect between a metal layer and the substrate.
申请公布号 US6774459(B2) 申请公布日期 2004.08.10
申请号 US20020216804 申请日期 2002.08.13
申请人 MICRON TECHNOLOGY, INC. 发明人 ROSSI GIUSEPPE
分类号 H01L27/08;H01L29/94;(IPC1-7):H01L29/00 主分类号 H01L27/08
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